The two companies announced today that they have taped out the first test SOC chip that is structured with 3D FinFET transistors, using Samsung’s 14nm LPE, or low power enhanced process .
Synopsys worked closely with Samsung to develop a test SOC chip that validates Samsung's advanced 14-nm FinFET process as well as Synopsys' DesignWare Embedded Memories using Synopsys' Self-Test and Repair (STAR) Memory System solution, the company said.
The test chip will enable the correlation of the simulation models to the FinFET process and incorporates test structures, standard cells, a PLL and embedded SRAMs.
The memory instances include high-density SRAMs designed to operate at very low voltages and high-speed SRAMs to validate the process performance.
Compared with traditional planar process, the FinFET process translates into significant power and performance benefits.
To tackle the challenge, Synopsys has worked closely with its chip design and manufacturing ecosystem partners to lay the foundation for the implementation of FinFET-based 3D transistors, including tool developers, foundries and early adopters.
Synopsys' highly accurate modeling technology helps to create its FinFET-ready Galaxy Implementation Platform.
The platform includes IC Compiler physical design, IC Validator physical verification, StarRC parasitic extraction, SiliconSmart characterization, CustomSim and FineSim for FastSPICE simulation, and HSPICE device modeling and circuit simulation.
"FinFET transistors can deliver lower power consumption and higher device performance, but they also bring tough challenges," said Dr. Kyu-Myung Choi, vice president of System LSI infrastructure design center, Device Solutions, Samsung Electronics. "We chose Synopsys as our FinFET collaboration partner to solve these challenges, because of our successful history together at 20 nanometer and other nodes. We continue to pool our expertise to deliver innovative FinFET solutions."