For more information, see PR News.
[sws_toggle1 title="PR News "> Synopsys, Inc. (Nasdaq:SNPS) today announced that Synopsys' IC Validator physical verification product has been qualified by United Microelectronics Corporation for 28-nm physical signoff, with immediate availability of design rule checking (DRC) and layout-vs.-schematic (LVS) runsets to UMC customers.
IC Validator, part of the Galaxy™ Implementation Platform, is the ideal add-on to IC Compiler™ for in-design physical verification, making it possible for place-and-route engineers to accelerate time to tapeout by eliminating late-stage surprises and manual fixes.
IC Validator is being actively used at process nodes ranging from 65nm to 20nm. UMC's qualification of IC Validator brings the unique benefits of in-design physical verification to design teams working at UMC's 28-nm process node.
"UMC is committed to making available to its customers solutions that ensure silicon success while optimizing design turnaround time. As such, optimal runset creation and efficient maintenance are of paramount importance," said SC Chien, vice president of Customer Engineering& IP Development Design Support at UMC. "Runset creation with IC Validator was completed in record time for our 28-nanometer process node. In addition, our IC Compiler customers can now take advantage of the productivity benefits of In-Design physical verification for faster design closure."
As feature geometries shrink, the number and complexity of DRCs needed to achieve manufacturing compliance is growing exponentially. IC Validator makes runset creation and maintenance effortless for users by providing a hybrid engine for processing checks based on both polygon and edge data.
Hybrid processing allows for efficient resolution of dependencies and more intelligent multi-core distribution, yielding faster runtimes.
Furthermore, IC Validator enables coding at higher levels of abstraction, streamlining tedious lower-level data processing.
Finally, IC Validator is architected for near-linear performance scalability that maximizes utilization of mainstream hardware, using smart, memory-aware load scheduling and balancing technologies.
Traditional physical verification done after design closure is no longer adequate for complex designs, causing late-stage surprises and leading to an increasing number of time-consuming and error-prone design iterations.
In-Design physical verification, based on intelligent integration between IC Validator and IC Compiler, makes it possible for place-and-route engineers to perform independent signoff-quality analysis earlier, before the design is finalized and while correction can be automated.
In-Design technology enables new high-productivity functionality, such as automatic DRC repair, timing-aware metal fill and rapid ECO validation, all within the place-and-route environment.
In-Design physical verification eliminates entire iterations with downstream analysis tools and maintains convergent design evolution to physical signoff.
"As manufacturing complexity places increased pressure on our customers to deliver within schedule, it is important that we continue to collaborate closely with leading foundries like UMC," said Antun Domic, senior vice president and general manager of Synopsys' Implementation Group. "This qualification brings the proven benefits of IC Validator and In-Design physical verification to UMC's customers working at advanced nodes." [/sws_toggle1]