The new transceiver card has been co-developed by Inova and the Intel Programmable Solutions Group, and enables engineers to easily set up hardware for testing and system development with the APIX2 automotive video interface. It can be connected to any Intel FPGA development board with a High-Speed Mezzanine Card or HSMC connector, which enables system development with Intel FGPAs and System-on-Chips or SoCs. A design example has been developed for receiving and merging APIX2 camera video streams and sending them over an APIX2 link, and will be available at the Intel Design Store.
APIX2 is Inova’s SerDes (serializer/deserializer) technology for video and data communication in vehicles. It provides high-speed differential data transmission over a quad twisted pair or QSTP cable, with bandwidth up to 3Gbps. APIX2 is the second generation of the proven Automotive Pixel Link or APIX standard, and is ideal for automotive display and camera applications.
Michael Hendricks, director for the automotive business in the Intel Programmable Solutions Group, said, “The APIX2 HSMC add-on card enables the interfacing of cameras and displays to Intel FPGAs via long-reach APIX2 interfacing, thus enabling the development of feature-rich next-generation cockpit experiences.”
The APIX2 High Speed Mezzanine Card can simultaneously stream multiple digital video signals, as well as 100 Mbps bidirectional Ethernet data traffic and SPI control data, over robust APIX cable connections into and out of a FPGA.
The two on-board Inova INAP375RAQ receiver devices accept video streams with resolutions of up 1600x600 pixels and refresh rates of up to 100Hz. Their flexible video interface is configurable to handle one or two independent video streams each, which gives a total of up to four video input streams.
The on-board Inova INAP375TAQ transmitter can send 18- or 24-bit video with a resolution of up to 1600x600 pixels, 24-bit color depth and refresh rates of up to 100Hz to a display using the OpenLDI digital video interface.
The card’s RJ45 10/100 Ethernet port enables it to send and receive data traffic over the APIX2 link of the transmitter and receiver #1, via a Media Independent Interface or MII. It can also be used to send IP video traffic over the APIX2 links.
In camera applications, the cameras can be powered remotely through Power over APIX or PoA using the card’s power regulator.
The APIX2 transmitter device includes an HSD or High Speed Data connector for a QSTP cable, as well as an LVDS interface via the HSMC connector from the FPGA.
Each of the two APIX2 receiver devices include an HSD connector for a QSTP cable. There is a parallel video interface of each receiver to the FPGA via the HSMC connector.
The new card also features an SPI port and STATUS pin connected to the FPGA.
The mezzanine card will be available in Q1 2017.