Hong Kong ( iTers News) - Computer, communications and consumer electronics technologies are rapidly converging to power and control a wide array of devices from automobiles to LCD TVs to wireless communications devices. So are a flurry of processor cores and other chip peripherals to create embedded processing chip solutions – a basic building block to power these embedded system devices.

Xilinx Inc. of the U.S. is now trying to cash in on the trend, because the embedded system market is where the programmability and processing power of its FPGA, or field programmable gate array technology are prevailing.

The fabless FPGA chip design house had already unveiled a new embedded chip solution called EPP, or extensible processing platform architecture that came complete with two ARM Cortex A-9 cores, Xilinx’s soft core and other peripherals like memory controllers on a single monolithic die.

The EPP is a 28 nanometer processing technology-based embedded solution platform that will allow Xilinx to go beyond its traditional addressable markets into a broad range of applications markets from low-power applications to bandwidth-extensive high-end applications.

In an interview with eNomad, Clement Cheung, director with marketing and applications of Xilinx Hong Kong Ltd., said, “The advantage of that (EPP) is that FPGAs allow your system to extend beyond what your processor provides. So, we call it extensible. There is a major difference between this platform and what was in the past.”

“Because of this new breed of products, we think, they can allow Xilinx to go into embedded markets, the area that we have never been before. They are automotive, digital cameras, consumers, LCD displays, and you can go into wireless communications like enterprise femto cells,” added he.

According to him, Xilinx plans to build an array of specific products around this EPP platform for the release in the first half of 2011.

The followings are excerpts from an Q&A interview with director Cheung.

As a growing of number of cars are now being built with infotainment system like media players, in-car entertainment as well as car networking system, they are requiring lots of

(iTers News)Could you tell us how Xilinx is tacking this requirement in the automotive markets, where you have built up strong presence?

(Cheung) Yes, that’s pretty much embedded, because you need processors. Traditionally, you always require MCU and DSP. Now, because processing requirements are higher, you need to process a lot of video and audio signals. For example, as you have a lot of sensors in the car, you need to make a decision on when to slam on brakes and how to control steering wheel and other stuffs. So, microcontroller approach is now not as effective as before. You need many of MCUs. So, people are tuning to FPAGS. Not only do FPAGs have DSP and processing capabilities, but also they are programmable. So, they can make changes very late into the design cycle. One of European cars like Mercedes Benz has as many as 18 FPGAs, Xilinx’s FPGAs.

They are good examples of increasing use of FPGAs. Now, FPGAs are in use for high-end cars, but even Hyundai and Kia are looking to FPGAs for mid-range applications, as well. So, FPGAs are going to be more and more common.

Design activities pick up in the Chinese automotive markets

(iTers News) How important are automotive applications for all of your FPGA product portfolios?

(Cheung) Automotives are one of our strongholds. We have very strong product line-up for automotive markets. We have Xilinx Automotive, or XA, which means all of our FPGAs are qualified for automotive standards called AEQ100.

Automotives are representing significant portions of total revenues, or double –digits. Especially in the past, most automotive design activities were coming out of Europe and North America by region, because they have design centers over there. Nowadays, we see that starting to move. For example, Delphi, which is one of the big US companies (automotive parts and components), started recruiting and hiring engineers in Chain. We can see that they are moving their design centers to China. So, this is a trend, because China is the biggest automotive markets in the world, zooming past the U.S. For the future, they will have more designs over here. And, also I think that very successful Korean car manufacturers like, Hyundai, Kia, and Daewoo are actually increasing their electronics contents

(iTers News)Embedded chip system markets are where the forte of FPGAs is. So, Xilinx has been building very strong presences in that area.

(Cheung) FPGAs have already crossed over embedded many years ago. If you look at existing FPGA, today we already a fully embedded 8 bit MCU cores, which is PicoBlaze – which is Xilinx’s proprietary MCU technology We have 32 bit version of that called as MicroBlaze, which is soft core. They have been used pretty common in with customers.

Xilinx also provides sets of tools called as embedded design kits, or EDKs, which provide one tool environment for embedded designers. They purchased our software tools and select embedded designs options. Designers can get every tool from debugger to simulation tools -everything for design environment.

Embedded is not new to FPGA. In the high-end side, Xilinx has PowerPC cores in our Vertex family of two generations. So, we have seen that embedded systems have been very important part of FPGAs. Moving forward, earlier this year, Xilinx announced a new embedded system solution, which we called as extensible processing platform, or EPP. This platform actually includes two ARM Cortex A-9 plus all the peripherals.

In the past, we didn’t have peripherals. But now, we have USB, PCIE, ICQS, and UI. All peripherals and standards are in the FPGAs. It is very powerful embedded platform, because ARM Cortex A9 is a mid-to high-end core that runs at a clock speed of 800 Mega hertz. We have two in every single device. We have two ARM hard cores, peripherals and one FPAG soft core in one single monolithic die.

Everything on a single monolithic die

(iTers News) What makes differences between your old embedded platform and EPP?

(Cheung) The advantage of that is that FPGAs allow your system to extend beyond what your processor provides. So, we call it extensible. There is a major difference between this platform and what was in the past. In the past, we also have processor core-in built FPGA. But, what is the major difference is that in the past the platform was FPGA-centric, which means you booted up FPGA first before you use microprocessors. Now, new EPP solution is processor–centric. In other words, even though FPGA is not powered up, you can still use processors.

You can use stand-alone processor. It has its own IO and its own interfaces. FPGA in the EPP is only a slave. ARM is the mater. ARM controls everything including FPGA. I think some of our competitors also have a FPAG plus ARM. But the problem is their FPGA is a master, while ARM is a slave, so, which is the opposite of most embedded system design environment.

The difference is that you have ARM on a PCB and FPGA on the next. You need a lot of connections between ARM and FPGA, which means using a lot of IOs. There are two reasons why we put two ARMs and FPGA on a single monolithic chip. One is to reduce the number of IOs. So, you can use the IOs for other user application. The second is latency. The latency between IOs FPGA and IOs of ARM (on two different PCBs) is very high. On a single die and single chip, the latency is shorter. It is very fast, so that you can do everything.

FPGA is a hardware accelerator for ARM. So, the platform also has one memory controller.

(iTers News) Could you more elaborate on other EPP features?

(Cheung) The other beauty of EPP is that FPGAs have DSP blocks. This is the very nature of FPGA. In other words, you can look at the system on a chip. You can have ARM, you have FPGA general logic and you can also use DSP. It has all three on one chip device. DSP will create tremendous processing power. For example, please look at such applications as matrix multiplications, matrix inversion and video processing, and those are very, very powerful features, which traditional ARM core doesn’t offer. It looks like you can always put together TI’s DSP, ARM and FPGA on a single chip. And it’s also programmable.

Because of this new breed of products, we think, we can allow Xilinx to go into embedded markets, the area we have never been before, including automotive, digital cameras, consumers, LCD displays. You can go into communications wireless. We are talking about enterprise femto cell and we are talking about basebands. Communications, they also need ARM core to do some monitoring functions. We can also go into audio and video broadcast, which you need processor as well. You can go into high-end industrial surveillance and medical imaging.

The applications are definitely very promising. We are now announcing a platform. The next step to go is that we will announce specific product family for EPP next year. This is platform is based on our Xilinx 7 series technology, which is a 28 nanometer process technology. And, you will have high-end part and low-end part.

Low-end & high volume applications are not where FPGAs prevail

(iTers News) If we look at embedded system markets, there are two different market segments – one for very traditional high-volume and low-end applications and the other for low-volume, but high-margin. Which segments are more fitted for FPGAs?

(Cheung) As for the traditional embedded system -we call it mainstream markets- we are focusing on 8 bit, 16 bit and 32 bit MCU areas. Those areas could be also our target. But, Cortex A9 is too powerful for those market segments. ARM 9 is enough. Xilinx chose ARM Cortex A9. The reason is that we want to serve that (low volume, but high margin) segment that requires significant processing power, which also can give pretty good leverage to our current FPGA technology.

For traditional very low-end embedded environment, we looked at what is the best value for this market. For example, the requirements are very different from high-end market segments. They do not need very powerful ARM cores. The second is they probably need very low standby power. They need very cheap chip solutions in the price range of 5 dollars. For those areas, right now, we do not have products at least for this moment.

I think power consumption is still one of the biggest issues that we as FPGA maker need to solve for the market segment-like this (traditional and mainstream low-end markets). So, handheld, set top boxes or gateways, those low-end areas have very high volume. However, those areas are first of all very competitive, prices are very low, and margins are very low, So, there are a lot of ASSPs available, as well. So, if there is an area, for example, which we thinks is software define and flexible, we think there will be very good values for us.

I think in cell phones space, because of iPhones and iPads, people are definitely seeing potentials for those markets. Those markets are now being well served by ASSPs and DSPs. People are looking for more information and more feature integrated into the phone, which means performance requirements are very high. Yet, the requirements for power are also increasing, too.

Programmable Imperative, ‘Unstoppable’

(iTers News) Where else Xilinx sees bigger market opportunities other than low-end mainstream segments?

(Cheung) What Xilinx is going into right now are undeserved markets which are not well served by ASSP, because ASSPs have their drawbacks-they don’t have flexibility. And, we are also trying to get into another underserved market that isn’t well served by DSP, because their processing power may be not high enough. Those areas, I think, will be good chance for Xilinx to go in. If we can use that as a foothold, maybe we can expand into the other areas.

In fact, if you look at the consumer electronics, even though FPGA, especially CPLD are not in handheld devices, FPGAs are very common in LCD and plasma displays. FPGA have been supporting most of these 3D movements in the LCD display, and are used with timing controllers as a bridge between different interfaces and even processing engines of LCD displays.

We have customers that are using Xilinx FPGA in their LCD displays today. We have been shipping about 6 to 7 millions of FPGAs for this market (LCD display). This is not a very high volume compared with cell phones, but very high volumes for FPGA. That represents good opportunities, I think, in embedded areas. People want 2D to 3D conversion, they want frame rate conversion and they want picture video enhancements. All of these features require a lot of processing power.

Many analysts are expecting FPGA to grow significantly in the next few years, outgrowing other semiconductor segments. We want to take the opportunities in what we called as programmable imperative. It is unstoppable. Basically, the requirements from the markets and the customers are that they want to do more with less.

You want more powerful products, but less power and cheaper. This is a requirement. Customers also require differentiations. They don’t want a cookie cutter solution. Maybe in the very low-end cell phones, they want turkey solutions. But, most of customers today want differentiations. FPAG allow differentiations and fast times to markets.

The reason is we are very successful in communications is because in the communications space, they need time to markets, flexibility and a lot of differentiation. FPGA allows them to develop their proprietary IPs on the device. This is a good value for them.

SSI; Moving beyond Moore’s Law

(iTers News) The toughest challenge facing the semiconductor chip maker is that Moore’s Law isn’t effective as it used to be before. How about Xilinx? Do you feel that in the same way?

(Cheung) There are some limitations in Moore’s Law, which stipulates the density of a chip doubles every 18 months, But, most of customers said that’ not enough. They want bigger and more power processor, which pack bigger number of cells, or transistors on a single die. I will give one example, Take our 65 nanometer technology, which is used with Vertex 5, for example, we have 330,000 logic elements in the biggest Vertex 5.

If you look at our 28nm technology, which we call as Vertex 7, which is two generations ahead, 330,000 logic cells are in a low-end density device. Our biggest device of Vertex 7 implements 2 million logic cells. So, the 40 nanometer, which is in between, the biggest element is 760,000 logic cells. You can see that, from 65 nanometers to 40 nanometers, the growth in density from 330,000 to 760,000 is about double. But, the migration from 760,000 in the 40 nanometers to 2 million cells in the 28nanometer is more than double in the number of logic cells.

What is challenge? Our challenge is our customers are pushing for bigger devices. Moore’ Law said you can only double in 18 months. So, what we will do? We develop technology called silicon stack interconnect, or SSI technology. Basically, having stacking technology allows you to put together smaller dies to make them big dies. It is not a monolithic solution. But, from users’ point of views, they feel like it is a big die. However, from Xilinx, we solved two technical challenges. One is we broke Moor’s Law. Secondly, it gives us better cost structure in yields because we all know that in order to yield bigger die, it will take time and more expensive That is why big dies always comes out with loss. This time, one big FPGA compromises of 4 different smaller dies. Die is much smaller which means we can yield die sooner, we can deliver products faster to customers. Also, as yield is better, it can give us better cost-structure, which means customers have better cost on bigger FPGA.

Those are innovations that Xilinx continue to invest to tackle the technical challenges.

(iTers News) How to tackle with power issues? What else is it that you are trying to differentiate from competition?

(Cheung) Power is very important feature requirements from customers. Every customer in your supply chain wants low power. How do you make low power? You involve many and many things. For example, with process technology, you need to reduce static power, but, to reduce dynamic power, you require architecture innovations. Xilinx has invested in many and many things. For example, we have invested in gate clocks, we have processor configurations. We have special design IOs that help save power. We have different transistor threshold voltages in what’s called as multiple threshold voltage to optimize power. We also have done several things. All this actually will help us to reduce dynamic power. We have software tool to do power optimizations, too. All this is actually helping our new family to improve power more than by 2X. For every family, we move down from 40 to 28 nanometers, we reduced power by more than 50%, which is very significant.

Equally Challenging

If you ask me we will continue to do that in every process node, I don’t know. It’s very big challenge. I guess the other challenge is that customers want productivity to get improved, too. We talked about power, performance, but productivity. At the same time, customers said power is good, performance is good, and we want to design it in half time, which means they want us to improve software run-time. They want to improve solution delivery time, IP delivery time. They want to migrate their IP from old technology to new technology faster. So, how do we do that?

Definitely, package innovation is one thing. So, we have this package. We also are looking at how to have one unified architecture. From our low-end to high-end device, we have one unified architecture, which allows customers to migrate smaller devices to bigger devices faster, because of the same architecture.

Vice versa, too. So, they can do a cost-reduction from high-end devices to smaller devices. If you look at our competition, they have different architecture- mid-end low-end and high-end, three different architectures.

But, in our case for 28 nanometer technology, we have unified architecture. We can make sure that customers migrate from IP to IP very fast. They are eager to migrate from 65, or 40 and 28 nanometer technology faster because using the same architecture. This will mean improvements in productivity for customers.

We are also looking at how to build targeting design platform or TDP, which mean we provide customers with not only boards, but also reference design and packages. Everything is put together in one open box experience. We build this TDP for specific market- wireless, medical, consumer, and industrial applications. And, we have specific solutions for different markets. You have software. Even IP is already loaded on the FGPA. On the menu everything is plug and play. Xilinx is the first FPGA company to do that. We call it productivity improvement for our customers.

They don’t have to develop, for example, memory controllers. All these standard things are in FPGA. Everything is already in the FPGA. Xilinx is changing the concept of usability. We hope we can improve design productivity of our customers. These are quite challenging to do, but quite simple, but not easy.

For example, all the boards, which Xilinx can provide, can work with other boards, too. For example, you have TI boards, Freescale boards, and Analog Devices board. They can connect together seamlessly with our boards, because we are using the standard interfaces, which we call FPGA measuring codes, or FMC, which is industry’s standard.

Heats can go nowhere

(iTers News) SSI technology has been around for years to do package-level integrations of multiple chips. What’s inside? What has driven Xilinx to implement it in the FPGA field? What benefits do you have or give customers in integrating 4 FPGA dies together on a single package, compared with one single bigger FPGA die? What’s a trade-off?

(Cheung) Technology concept is not a brand new. Basically, we are the first one to apply it in FPGA. The difference this time is that FPGA is actually a very high performance device. We were talking that the chip is running at 800Mhz. We have very high-speed IOs on the device. So, we need to ensure first of all latency between difference slices is very short. This is very key- latency issue. Second challenge is we need to ensure it is very reliable. That’s why we use concept of silicon interposer. TSMC is one of them to develop this silicon interposer

First of all, silicon interposer does not any transistor. It is a passive component. Because it doesn’t have any transistors it is very easy to manufacture. It is based on a very matured 65 nanometer technology.

The difference is that it has a lot of wires in the interposer. So, we can connect FPGA slices together. It also contains what we call as ‘through silicon vias’, TSV technology, which allows you to connect this die to the substrate-package substrate. The challenge is how to increase reliability of this TSV and to fill this TSV with conducting materials. The technique to do that is patented by TSMC. It’s not easy to do because you can’t dump your conducting materials. You need to consider reliability and because it is edge. TSV is a hole of edge. You make sure it doesn’t shortcut other devices.

The other technology is micro-bumps that connect other FPGA dies to this interposer. With the micro-bumps, you need to make sure that all connections can sustain stress. The good thing about the interposer is the same materials as that of die, even though they are different technologies. But, they are same silicon materials. So, it expands and contract at the same time That’s why the stress to this micro-bumps is kept to minimum.

With TSV, micro-bumps and silicon interposer, we put those 4 FPGA dies side by side, but don’t stack them. The reason is that FPGA has a very high frequency operation so that power consumption is very high. If you put them on top of each other, heat can’t go anywhere. Heat can go only side way. By doing that, we can remove the heat issue.

(iTers News) What benefits do you have or give customers in integrating 4 FPGA dies together on a single package, compared with one single bigger FPGA die? What’s a trade-off?

(Cheung) The other thing is that if you stack dies, you need to have new design flow, because signal goes horizontally and vertically. There is no such 3D tool available in the market. And you put them side by side, signal go from this die, going down the interposer, and then up this die and down again, still horizontal, which means you don’t need to change software tool and our design tool.

That is one of the innovations, too. Stacking with dies with silicon interposer is 3D in that sense. This is definitely a result of multiple vendors basically helping this SSI technology to come true, or be reality.

Xilinx basically designs FPGA, design interposer, the package, but we do not manufacture them. But TSMC manufacture FPGA, interposer, TSV technology. And then, IBIDEN provide package substrate. AMKOR put all these things together, and also provide micro-bumps.

AMKOR is the original owner of the micro-bump technology.

All these companies work together to provide final products. The advantage of SSI technology that it has tens of thousands of routing connections, and latency is only one nano second from die to die. It’s very short and very high performance.

Yield curve is another important benefit. Traditionally, yield is in proportion to size (the number of cells or transistors). The bigger the size is, the lower the yield. In order to two million logic cell dies, your yield is always down here. As process technology improves, yield will improve. If FPGA has large number of logic cells, your yield is very low, compared to other size with smaller number of logic cells.

What we are doing here with this SSI instead of one monolithic die is that we make it with four smaller dies, each of which have only 25% of two million logic cells of one big monolithic. So we can make them smaller, which mean yield improvements  that much. The yield of this small die is much higher than that of this big die.
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