(iTers News) - Crack open Altera Corporation’s newly released Stratix 10 FPGA & SOC solution, and you can figure out why PC microprocessor chip giant Intel acquired the world’s second largest FPGA chip maker in a US$16.7 billion deal.  

The Stratix 10 is the latest and the most advanced of Altera’s high-end FPGA family that was designed not only to address traditional FPGA market like optical networking and broadcasting equipment, but also tap into newly emerging market like data center servers.

Especially, the Stratix 10 sets a precedent for how FPGA chips of today will work together with a CPU to address new daunting application requirements for faster data searches, as data centers across the world are struggling to keep up with their customers’ strong clamor for far faster searches and data analysis.

Fabricated with Intel’s 14nm FinFET 3D transistor process technology, the FPGA chip solution is also a reminder of how crucial Altera's silicon fabrics are in Intel’s future technology roadmap that sets its sights on consolidating leadership in data server market and advancing other new application markets.

“The problem that data center customers try to solve is a very fast look up or very fast search or uploading Xeon (Intel CPU for data center servers) for application acceleration, or computational acceleration. To do that, to achieve what they really want to do requires many FPGAs. The performance of today’s (FPGA) architecture, because of wider pipe, is constrained and limited. In Stratix 10, because of higher density and performance improvements, we can go from 5 to single FPGA. Of course, if you do that, you can save a lot of power, and are able to meet the throughput which the acceleration requires from for the Xeon processor. It is a good solution for data center,” said Patrick Dorsey Sr.Director of Marketing Component Products Altera Corporation

Traditionally, FPGA chip solutions have been working as a hardware accelerator to speed up the functions and performances of CPUs in wired and wireline optical networking equipment. Yet, data centers are newly emerging as new application market for FPGAs, as strong customer requirements for faster boot up of data-intensive images and videos are opening up new opportunities for FPGAs to replace GPUs.

True enough, GPUs have been mainly working together with CPUs in a data center server to help perform what’s called as a floating point multiplication acceleration to search for image and video data.

Yet, GPUs consume lots of power, letting energy drain down data center servers – the most challenging issue facing data centers.

That’s where the forte of the Stratix 10 comes in. It outperforms GPUs, while consuming less power.

The Startix 10 family’s hyper flex architecture is the technology enabler that allows it to achieve two times gains in the core performance, or a 1 GHz speed, compared with its predecessor Aria 10’s 500MHz. It also reduces power consumption by up to 70%.

The hyper flex architecture is all about how to make the routing delay as short as short. Altera had done this putting millions of hyper-registers everywhere on the routing or fabric. The ubiquity of registers, a storage component in a function blocks, allowed the Stratix 10 to split the typical routing delay time, which it takes data to go from one logic block to another, by three.

“We can fix, or improve this 3.5 nanosecond routing delay. We do that by ensuring the longest delay short. Instead of 3.5 nano seconds (which it typically takes to transfer data from one functional block to another), we have 1.2 nano-seconds plus 1.1 nano-seconds, plus 1.2 nano seconds. Still it takes 3.5., but now, as 1.2 determined the performance, the performance goes up dramatically, " said Senior director Patrick Dorsey.           

He came up with one analogy to describe this concept. “Think about one big bridge. The bridge can hold only one car. Then you have one hundred cars over the bridge. You have 99 cars waiting until one car finish crossing. Here, we three smaller bridges, you can have multiple cars going over the same time you can get more cars through in the same period of time. This is very simple but the powerful concept to double the performance, or more.

Sure enough, one of the biggest impediments in increasing the performance of FPGA solution is the size of the routing delay. To tackle the challenge, FPGA chip makers have introduced wider data bus, or interface, because system performance is all about getting data through a chip from one side to the another as soon as possible To get more data, they tried to make the bus far bigger to push more data through.

Yet, the trade-off is the big traffic congestion. As lost of resources are clamoring for their turn to get data on the wider bus, it created congestions. So, FPGA chip makers have been struggling to make the bus shorter to solve the bandwidth problem.

“That ‘s what we want to say about 2x high performance with HyperFlex technology, and so big changes in the FPGA technology can do enable both very high performance and also very good power efficiency, “ stressed Senior director Patrick Dorsey.     

Altera’s innovations in the power saving technology don’t stop there.  The chip maker has implemented what’s called as smart voltage ID technology to cut down energy bills. Originally designed and patented by Intel Corp., the smart voltage management technology allows processors or FPGA chips to tell the PM IC, or power management ICs of how many voltages they need to run their optimal level application.

“This capability enable things like 10 teraflops in  a single chip or 8 teraflops per watt, which gives a magnitude of 10 x better performance and power capability than a GPU in application like data centers,” added he

The smart voltage ID technology can help save 20 to 25% in the dynamic, active power consumption, according to Altera.   

What makes the Stratix 10 more stand out from competition is its heterogeneous system architecture, or HSA. Coming complete with ARM Cortex-A53 processor and FPGA fabrics in a single piece of silicon die, the Stratix 10 comes in a so-called SiP, or system in package allowing the chip maker to pack multi dies into a single package.

The multi-die single chip package HSA design concept is to enable system developers to easily accommodate changes in data communications protocols and other technology standards.              

“The reason why we need multi dies here is to tackle a challenge. The challenge here is a data rate in the transceiver or the pin, which talk in very high speed to other devices. The range of data rate is getting very broad. This is very complicated problem to solve in a single chip. W need to wait to solve the problem, “said Senior director Patrick Dorsey.   

“Another problem is that the standards in the markets. Many are not ready yet to be hardened in the silicon. For example, Gen 4 PCIe is not done yet.  The standards are not done. We need solutions to allow us to support protocols not standardized yet. The third problem is that, to support this data rate, different modulation schemes are required. These are Altera’s problem in meeting customers’ needs. What we are doing with Stratix 10 that we has created the solutions which are flexible, scalable, and enable for fast introduction of products, " added he.

The Stratix 10 is a monolithic single FPGA die incorporating all the fabrics in a one die, but it is surrounded or packaged together with multi dies, or what’s called as tiles. The multi die has hardened IPs, or ASIC IPs for protocols and high speed transceivers. The key benefit here is that the chip maker can add capability to the tiles by replacing it with other capability without creating large new FPGA die. This gives the Stratix 10 flexibility and scalability to change number of tiles based on costs and performance needs.

At the heart of the SiP technology is EMB or embedded multi-die interconnect bridge technology, which is owned by Intel Corp.

The technology is known to be much more efficient than a 3D silicon interposer technology or rd 3D TSV (Through Silicon Via Hole). The technology is a dedicated piece of silicon for connectivity for which Altera claims doesn’t have reliability and cost issue available in a large 3D silicon interposer technology.

Enhanced security is the last piece of the innovation that Altera has embedded in the Stratix 10. As users of FPGAs are integrating more of the systems into a single FPGA chip there are strong requirements to treat different functions separately, and secure them independently.

To meet these requirements, Altera has ported what’s called as Secure Device Manager, a sector –based authentication and multi-factor authentication and encryption technology.

“Basic concept we out is SDM secure device manager. It is a processor-based configuration security approach. The benefit here is that in the Xilinx architecture and previous Altera architecture, configuration was a fixed function, a static and determined approach.  That didn’t allow customer to securely configure FPGAs based on applications. With the Stratix 10, because the configuration is based on a processor, every configuration can be unique, and therefore, more secure. The key idea is here a customizable configuration, a processor-based configuration, not determined by Altera, but customers,” Senior director Patrick Dorsey.   

Coming built with more five million logic elements, or Les, the Stratix 10 is scheduled to go for sale by year-end