Synopsys' Foundation IP on TSMC's 40nm eFlash processes implements unique features that enable designers to reduce power consumption for IoT designs.

The logic libraries include multiple channel gate lengths and ultra-low leakage standard cells to minimize leakage power, and offer power optimization kits and multi-bit flip-flops to achieve near-threshold operation down to 60 percent of nominal voltage.

The embedded memories offer light sleep, deep sleep, and shut-down power management features for the lowest leakage, as well as assist circuitry to enable the lowest operating voltages.

The DesignWare Logic Library and Embedded Memory IP on the TSMC 40nm eFlash processes is available through Synopsys' Foundry-Sponsored IP Program, which enables qualified customers to license the IP at no cost from Synopsys.

"TSMC continues to build on our long history of collaboration with Synopsys to deliver high-quality, proven DesignWare IP on a wide range of TSMC processes that help our mutual customers achieve their design objectives," said Suk Lee, senior director of design infrastructure marketing division at TSMC. "The availability of Synopsys' Foundation IP for our 40nm eFlash processes demonstrates how Synopsys continually invests in developing IP that enables designers to achieve the best power and area for their SoCs."

"Synopsys and TSMC have worked closely together for many years to understand designers' specific performance, power and area requirements for their target applications," said John Koeter, vice president of marketing for IP at Synopsys. "By offering foundry-sponsored DesignWare Logic Library and Embedded Memory IP with differentiated low-power features for TSMC's 40ULP eFlash and 40LP eFlash processes, we are enabling designers to improve energy efficiency and extend battery life of their IoT products."

DesignWare Foundation IP for TSMC's 40ULP eFlash and 40LP eFlash processes is scheduled to be available in 2017 at no cost to qualified licensees as part of Synopsys' Foundry-Sponsored IP Program.

Highlights

• DesignWare Logic Libraries offer power optimization kits, multi-bit flip-flops and ultra-low leakage standard cells to achieve lowest power with near threshold operation


• High-density DesignWare Embedded Memories provide advanced power management features, a low leakage periphery option and assist circuitry for lowest operating voltages


• DesignWare Foundation IP in the TSMC 40nm LP and ULP eFlash processes is a part of Synopsys' Foundry-Sponsored IP Program, and is available to qualified licensees at no cost