(iTers News) - Developed to compress 4K and high resolution video contents, the next generation video standard HEVC/H.265 brings 50% bitrate saving, compared to content encoded with H.264/AVC.


Requirement of TV broadcasting for carrying 4K and ultra-high definition content is now driving the adoption of the HEVC or  High Efficiency Video Coding standard.


This demand for devices supporting HEVC is growing fast, and Allegro DVT is ready with the industry’s first fully compliant HEVC decoding IP that supports both Main and Main10 profiles. The Main10 profile was specifically designed to improve 4K content video quality thanks to 10 bit color depth support.



Its HEVC decoding IP is available today, runs real-time on FPGA and can be immediately delivered to any customer wishing for 4K enabled products. We see that 4K content will drive the market of next-generation ultra HD television displays (UHDTV) and content capture systems. Our customers have an immediate requirement for HEVC into System on Chip (SoC), which we are ready to address with our HEVC Decoding IP.


One of the major innovations in the HEVC standard, is the introduction of several tools to parallelize processing, such as “dependent slices”, “tiles” and “wavefront parallel processing”. The HEVC decoding IP is based on a scalable and unique multi-core architecture, supporting any combination of these parallel processing tools. This unique decoder architecture removes all constraints on the encoders and ensures interoperability with all types of parallelized encoding.


The HEVC decoding IP core is designed to be easily integrated in all next generation SoC devices requiring exceptional performance while maintaining a very low operating frequency and high level of power savings.


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