(iTers News) - Synopsys, Inc. has taped out of a broad portfolio of DesignWare Interface and Foundation IP on TSMC's 10-nanometer FinFET process.

The tape-out will enable chip designers to accelerate the development of SoCs that incorporate USB 3.1, USB 3.0, USB 2.0, HSICPCI Express 3.0, PCI Express 2.0 and MIPI D-PHYinterface IP.


In addition, Synopsys is developing embedded memories, DDR4, LPDDR4 and MIPI M-PHY IP, which will further extend its 10-nm IP portfolio.


TSMC's 10-nm process boasts of 2.2 times the logic density, a 15% performance improvement, and 35% power reduction, compared to its 16-nm FinFET Plus process node.


Taking advantage of the process, Synopsys has re-architected its IP at 10 nm for lower power, higher performance and smaller area compared to the previous generation.


As an example, the high-speed SerDes-based PHYs consume less than 5mW/Gb/lane.


"As the leading provider of physical IP, Synopsys has collaborated with TSMC on the development of IP for the 10-nanometer process, enabling designers to achieve the design goals of their next-generation SoCs," said John Koeter, vice president of marketing for IP and prototyping at Synopsys. "By offering a broad portfolio of IP at the TSMC 10-nanometer node, Synopsys is reducing the risks associated with moving to this new process technology."


"Synopsys' track record of providing high-quality IP through many generations of TSMC processes, including 10 nanometers, offers designers a low-risk path to integrating high-performance IP into their SoCs," said Suk Lee, TSMC senior director, design infrastructure marketing division. "Our close collaboration with Synopsys on the development of IP for the TSMC 10-nanometer process enables our mutual customers to reduce their power and area, increase performance and accelerate their time to volume production."


Front-end kits for DesignWare IP on the TSMC 10 nm process are available now.

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