(iTers News) - Moore’s Law continues delivering and chip designers continue to make use of the ever more sophisticated technology. At this year’s International Solid State Circuits Conference, papers describe progress made possible by Intel’s leading 14nm process, including the first complete wireline transceiver on 14nm technology (60 percent smaller than the smallest comparable link) and the world’s smallest SRAM bitcell, reducing peak write power by 24 percent compared to actively biased circuits. Intel Labs presents research in chip design to boost performance and energy efficiency. This includes a graphics execution core for SoCs with an 82 percent reduction in energy consumption at near-threshold voltage and 75 percent higher frequency at maximum performance. For more, see descriptions of many of Intel’s activities at ISSCC.