Hynix Wafer Line

(iTers News) – What’s referred to as a manufacturing process, or design rule is all about how tiny a semiconductor chip is, how fast it is processing data, and more importantly, how thriftily it consumes power. Called after the distance between transistors that form the circuitry of a chip, as a result, the numeric indicator of the design rule such as 30, or 40 nanometers is the industry’s fundamental measure of how competitive and profitable a chipmaker is. As applications markets for semiconductor chips are rapidly diversifying beyond PCs and fragmenting into mobile phones, smartphones, tablet PCs, and netbooks, however, the 40 year-old rulebook is now being rewritten, requiring chip maker to do more than just to work on the design rule.


Rewriting the formula is Samsung Electronics Co., Ltd, a memory chip technology bellwether. “Since 2010 when a sudden sprout of iPhones and iPhone-like smartphone clones started to dismantle the so-called Wintel duopoly’s decades-old reign on PC OS and CPU platform market, the industry’s rule of the game has dramatically changed, “ said Seoungbak Lee vice-president with PR and communications team of Samsung Electronics. .


“In the old says, all you have to do to outperform competition was just to keep ramping up your manufacturing process, as the ramp-up enabled you to get more chip out silicon wafer. Yet, the new rulebook of today is requiring chipmakers to work extra technology wonders to stay competitive. Especially when it comes to DRAM chips, Samsung is now scrambling to change the way that chips are designed and etched to satisfy extremely demanding market requirements for far faster, but a lot power-thriftier DRAM chips,” added he.


According to him, its power-thriftier “Green” memory product line-up is just the upshot of its extra design work, demonstrating how differently Samsung is designing and fabricating DRAM chips from other rivals.


Do more than just the basics


Under its new design scheme for “Green” memory chips, for example, Samsung chip design engineers set a performance benchmark for power consumption and access time speed higher than what they can achieve with the design rule alone, and then work extra jobs around memory cells to meet the performance target.


Here is an example of how and where they go extra miles. Crack open a DRAM chip, and you can find a matrix of memory cells sitting in row and columns as well as four tiny traces, or lines squarely surrounding it.


The design rule is all about shrinking down the cell size, of which each is made up of one transistor and one capacitor.


Yet, where Samsung work extra hours to change the way of chip design is the surrounding area that is termed as peripherals in the industry’s jargon.


The peripheral area is where there used to be data paths, or buses, an interface line to bring back and forth data between memory cells and a CPU.


Yet, Samsung Electronics traces and etches more lines there to add in logic controller circuitries that can not only help speed up data-in and-out, or access time, but also dramatically cut back the frequency of what’s called as the capacitor refresh time.


Samsung Austin Aerial View


Cut back on refresh time


The role of the capacitor of a memory cell is to store data, but the very basic disadvantage of the capacitor is to lose data easily if it’s not recharged, or refreshed at a certain interval. That drawback results in tremendous power loss and a mismatch with the speed of a CPU.


Samsung is working technology wonders of further accelerating chip speed and cutting back on power consumption by letting the controller circuitry to lengthen the interval of refreshing as long as possible.


“We have done this extra work at the expense of productivity, because putting more circuitry around the matrix of memory cells makes the chip size far bigger, leading to less number of chip output per silicon wafer than otherwise. Yet, we get rewarded, because we can charge premium prices for that add-on value. This helps partly explain why Samsung has weathered out one of the industry’s most tumultuous years of 2010 and 2011 ending up staying profitable, “ said vice president Lee.


The strategy proves right.


Samsung’s earlier-than-competition ramp up to a 30 nanometer-class design rule for DRAM chip production and its new way of chip design have combined to help the company profit out of one of the industry’s worst nightmares that have all of other rival chips drowned deeply in the sea of red ink.


Samsung’s extra design work is paying off in other ways, too.


Take a 30 nanometer-class technology for example.


As Samsung specified a performance standard for a DRAM chip of 30 nanometer geometry higher than a normal 30 nanometer-class technology defines, the heightened entry barrier came at the expense of other chip makers’ yield –the percentage of the marketable chips versus total production.


They struggled to match Samsung’s performance benchmark, but only to see their yield fall below expectations, forcing them to drag their feet on their roadmap to start volume production of a 30 nanometer-class DRAM chips.


Hynix Wafer Line 3


One of the notable victims is Samsung’s backyard arch-rival Hynix Semiconductor Inc., which developed its own 30 nanometer-class technology early in 2011, but struggled to improve yield all the way through the year.


Hitting what’s called as golden yield at best in the end of 2011, Hynix is now producing about 40% of its DRAM chip output with its own 30 nanometer design technology.


“We are racing one generation behind Samsung in design technology ramp-up, while others elsewhere in Japan and Taiwan are lagging two generations behind. The entry barrier to the 30 nanometer–class technology was higher than we had expected, “ James Kim, director and head of IR team with Hynix Semiconductor said.


Go extra miles


“What made differences with the past was that we faced harder times designing peripheral areas. To catch up, we will have our indigenous refresh time controller circuitry on hand by year-end. I agreed that’s what we have to break through,” added he.


The market is trending in favor of Samsung’s design scheme, too. As more and more consumers are clamoring for more powerful CPU and OS platform to run data-rich apps on a high-definition screen, a growing number of smartphones and tablet PCs are being built around dual, or quad-core CPUs, matching the performance level of genuine PCs.


At the same, consumers are calling for longer battery life to entertain and work on the go. .


That will likely require far roomier data storage space per system for video buffering, fueling demand for power-thriftier LP, or low power DDR2 DRAM chips.


For example, Samsung expects high-end, premium tablet PC will incorporate a 2GB DRAM module per system as main memory system.


To cash in on the trend, Samsung plans to mainly ship 4Gb LP DDR2 DRAM chips of 30nanometer-class geometry as well as 4Gb LP DDR3 DRAM chips of 20 nanometer-class for smartphones and tablet PC markets in 2012.


As microprocessor chip giant Intel are rapidly turning to what’s called as ultrabook – a sort of ultra mobile PC- to drive up long-dormant PC replacement demand, that tiny, but powerful mobile PCs are another sure-bet that Samsung is pinning its hope on for 2012.


Especially, ultrabook will likely spur soaring demand for SSDs, or solid state drives, as a growing number of them will displace HDDS to incorporate the Nand flash memory chip-based SSDs as their main external storage devices.


Hynix Wafer Line Image Cut


Yet, SSDs are still selling for 4 or 5 times as high as HDDs. At issue is how to cut down manufacturing costs.


The only way out is to dramatically improve productivity by getting more of SSDs out of silicon wafer.


Today, most chipmakers are churning out about 10 SSDs out of 300 mm silicon wafer on average. A. Once the productivity hit the level of 1,000 SSDs per wafer, Nand flash memory chip makers can build economies of scale to match the price of HDDs.


Ultrabooks emerge as next bet


It won’t be until 2014 that SSDs reach a crossover point where their prices first match those of HDDs, and then fall below exponentially, according to market analysts.


To accelerate price cut-downs, Samsung is working out a new technology breakthrough to etch and build a Nand flash chip in 3D, 3-dimensional architecture.


The 3D architecture technology is often likened to building lofty multi-complex buildings, if current 2D etching technology is likened to 2-or 3 story buildings.


The chip maker is fabricating the vast majority of Nand flash memory chips with a 20 nanometer-class technology. Volume production of 10 nanometer Nand flash memory chips will start sometime in the first half of 2012.


Hynix Semiconductor is bullish about the growth potential of SSDs, too. The chip maker stay still profitable selling Nand flash memory chips.


To cash in on the potential, the world’s second largest memory chip maker plans to allocate more of its wafer resources for production of Nand flash memory chips.


With 100,000 wafers allocated for production of Nand flash memory chip per month, they accounted for about 30 % of total revenues in 2012.


Its mainstream manufacturing technology for Nand flash memory chips is a 25 nanometer design rule.


When it comes to DRAM chips, however, Hynix turns bearish, as chip inventory is still piling up.


As the chipmaker sees no sign for recovery in DRAM chips, Hynix expects the unit contract price of a 2Gb DDR3 DRAM chip will a little bit move up and down around US$85 cents for a while.


To squeeze out profits even selling 2Gb DDR3 DRAM chip below US$1, Hynix plans to mix up its 30 nanometer-class technology and 29 nanometer design rule to produce the vast majority of DRAM chips.


Its goal is to fabricate more than 65% of total DRAM chip production with a 35 nanometer-class technology by year-end, while producing the rest with the 29 nanometer technology.


The well-balanced product mix-up strategy will also help the chipmaker to turn profit. The chipmaker is now generating about 25% of revenues from relatively lucrative mobile applications selling 2Gb LP, or low power DDR2 for two times as high as commodity 2GB DDR3 DRAM chips for PC markets.


As a percentage of total revenues, shipment of DRAM chips to lucrative server and graphics applications markets represent 10%and 15%, respectively.


 


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