(iTers News) -Toshiba turns up heat in the competition for 3D NAND flash memory chip market starting sample shipments of a 64-layer BiCS 3D NAND flash memory chips.

Incorporating 3-bit-per-cell that translates into reading or writing 3 bits of information on every clock cycle, the 64-layer vertically stacked NAND flash chips has a storage capacity of 256 gigabits.

The 64-layer 256 gigabit chip is the newest of Toshiba’s 3D NAND flash memory following its rollout of 48-layer BiCS NAND flash chips.

BiCs is Toshiba’s trademark for its proprietary 3D NANd flash memory chip technology, standing for bit cost scaling.

Once in full production, Toshiba’s roll out of the 64-layer NAND flash memory chips will likely threaten to undermine Samsung’s 48-layer counterpart on costs. The higher the stacked memory cell layers go, the more bits they can store. Compared with Toshiba’s 48-layer NAND flash memory chip, for example, it has 40 % more storage spaces of bits, which translate into cuts in what’s called as bit cost, or costs per bit.

Under a planar 2D NAND flash chip, the 3D NAND flash chip stacks layers above layers of control gates that are connected by word lines as high as 48 or 64 layers depositing silicon dioxides in between control gate sheets. The next step is to punch an array of holes through the control gate columns to the bottom of the wafer substrate using one photo mask. The inner walls of the hole is then coated with silicon dioxide to create dielectric gates between control gates and charged trap gates where information is stored. The final step is to deposit silicon nitride on the silicon dielectric layers to form charge trap gates.  To form tunnel dielectric or channel gates, another oxide layer is deposited on the silicon nitride layers.

Unlike floating gates in the 2D planar NAND flash memory chips that are conductive layers, the charge trap gates are insulated layers that help greatly reduce signal interference between memory cells.
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