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Entegris ÀÎÅױ׸®½º ±âÀÚ°£´ãȸ semicon korea 2016

Entegris regional director Chris Lim
semicon korea 2016



3D chip-stacking technology like 3D FinFET transistors and 3D NAND flash memory chip, and double patterning technologies are all about the way how to make chips faster, smaller, and power-thriftier with no resort to conventional chip-scaling technology

As the conventional chip scaling technology is nearing limits in shrinking the geometry of chips below 10nm node, chip makers are turning to other alternatives for keeping the industry’s Holy Grail Moore’s Law alive - an observation that the number of transistors would double every 18, or 24 months. .

The industry’s embrace of new alternative 3D transistor chip technology is opening up new market opportunities for semiconductor raw material makers, as the implementation of 3D chip stacking technologies have more to do with innovations in raw materials and chemical compound formation.

True enough, semiconductor raw material makers are today seeing market opportunities and challenges at the same time, as the industry’s ramp-up to 20nm and below node technology has been creating demand for new breed of chemical gases, new chemical compound, and new set of chemical formation formula.

The challenges will become more compelling,  as the industry is rapidly adopting 3D architecture chip-making as well as 3D chip TSV packaging technology

“As the chip scaling and photo lithography technology has been going from 60nm node down to somewhere near a 10nm node and belwo, the chip makers are today going through about 2,400 steps of chip-making processes to fabricate chips on a silicon wafer. That is an exponential jump from 700 steps they had undergone a couple of years when they grappled with the 60nm node technology processes. So, how to formulate or develop defect-less, or pollution-free chemical gases and compound is more at stake than manufacturing equipment themselves in fabricating chips in a golden yield, “ said Chris Lim, regional director with Entegris, Inc.

“Especially, the industry’s embrace of 3D chip-stacking and 3D-chip packing technologies is posing more challenges and opportunities,” added he.

According to him, the  semiconductor chip industry just focused on the conventional chip scaling technology in the past to improve yield -the ratio of the marketable versus total production, but as the geometry technology hits wall, the industry is looking to alternatives like 3D chip-making and packaging technology tor structure, more relying on material solutions than chip scaling equipment.

Entegris Inc. is a U.S.-based total solution provider that supplies a wide range of products from chemical containers to yield-enhancing materials and solution for semiconductor manufacturing. The company is market leader in contamination control, critical materials handling, and advanced process materials for chip-making and other hi-tech industries.

A case in point is PR, or photo resist materials, which are coated on a slice of silicon wafer to develop and thus create the circuitry pattern of a chip. As the width of the chip circuitry is getting as small as 20nm and below, the chip pattern get more breakable when it is developed. The growing vulnerability requires a wholly different bunch of PR materials, of which viscosity is much stronger. The higher the viscosity is, the less breakable the circuitry pattern is.

The fabrication of the 3D NAND flash chip is another example of how complex the chip-making processes, as the 3D chip have layers over layers of transistor cells stacked in a 3D structure.

“The 16-and 32-layered 3D cell structures translate into increases in the chemical vapor deposition and ion implantation processes, compared with 2D planar NNAD flash memory chips. Whenever one process is added, it demands new materials.  For example, the 3D NAND flash memory chip  makers are struggling to find another chemical solution and process alternatives to current etchant and H-process, which are used in 2D planar chip, it is fueling demand for new chemical materials,” explained.

The same is true of 3D TSV, or through silicon via packaging technology. The TSV technology is a sort of wafer to wafer chip packaging that binds together chips via an ultra-tiny microscopic hole. To do that, chip makers first have to attach two fabricated wafers back to back and then separate them. As with the case, the wafer to wafer packaging requires extra processes and new materials like resin and polymers.

post CMP



As the chip node goes down somewhere near to 10nm circuitry, post-CMP, or chemical mechanical planarization process is getting more and more complex.

For example, chipmakers are adding new materials like cobalt and tungsten to make interfaces among transistors as they grapple with 10nanometer node. The process complexity requires new type of CMP materials to polish and clean silicon waters with damaging advanced films or new materials.

That’s the reason why Entegris has recently released a new product family of PlanarClean AG.

Designed to be used in 10nm processes, the PlanarClean AG family is a sort of formulated solutions that guarantees superior cleaning in advanced processes that use copper, cobalt and tungsten without compromising new materials ad thin films. Its propriety formulation offers increased performances through enhanced reliability and yield, low to zero corrosion and defects and increased queue time.

The CMP process is a sort of a mechanical polishing step that utilizes a chemical slurry formulation to remove unwanted conductive or dielectric materials from the surface of the integrated device to make it flat and smooth to build additional layers of integrated circuitry.

The post-CMP cleaning step removes nanoparticles to minimize potential wafer defects while maintaining the integrity of the layers of materials already in place.

Changes to the number and types of films and materials exposed during cleaning in advanced processes have highlighted a need for specifically formulated cleans. In addition, changes to the particles used in slurries have rendered many of the traditional post-CMP cleaners ineffective and inefficient for leading-edge technologies, specifically in Front-End-of-Line (FEOL) processes.

These challenges are now forcing chip makers to prefer formulated cleans to commodity cleans.

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